1. Technical Field
The present invention relates generally to the field of semiconductor processing and, more specifically, to finFET CMOS devices.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in complementary metal oxide semiconductor (CMOS) technologies such as in the design and fabrication of field effect transistors (FETs). FETs are the basic electrical devices of today's integrated circuits and are used in almost all types of integrated circuit design (e.g., microprocessors, memory, etc.). FETs may be formed on conventional substrates. For example, a conventional CMOS FET formed on a silicon wafer may include a gate oxide layer formed on the wafer, a gate formed on the gate oxide layer, spacers formed beside the gate on the gate oxide layer, and doped source/drain (S/D) regions arranged on respective sides of a gate conductor. The gate is separated from a channel (which is situated between the S/D regions) by the gate oxide layer. Shallow trench insulator (STI), local oxidation of silicon (LOCOS), or poly-bared LOCOS isolations are usually employed to provide for isolation of adjacent transistors. When the FET is operated, an electric field is grated by applying a voltage to the gate. The electrical field is used to control the channel situated between the S/D regions. For example, if the channel is turned on, the electrons/holes flow from the source region to the drain region. In contrast, if the channel is turned off the electrons/holes cannot flow between the source region and the drain region. Therefore, the on/off state of the channel controls the connection/disconnection of the circuit.
Unfortunately, increased device density in CMOS technologies often results in degradation of reliability. One type of FET that has been proposed to facilitate increased device density is a double gated FET (finFET). FinFETs use two gates, one on each side of a fin body (i.e. transistor body), to facilitate scaling of CMOS dimensions, while maintaining an acceptable performance. In particular, the use of the double gate suppresses Short Channel Effects (SCE), provides for lower leakage, and provides for more ideal switching behavior. In addition, the use of the double gate increases gate area, which allows the finFET to have better current control, without increasing the gate length of the device. As such, the finFET is able to have the current control of a larger transistor without requiring the device space of the larger transistor. However, conventional fin height control techniques have drawbacks that introduce undesirable variation into the height of fins. For example, conventional non-silicon-on-insulator finFET technologies rely on a silicon etch-stop height control technique for determining fin height. This technique involves the process of etching fins from silicon where the silicon fins have different heights. The height of a fin is determined by how much bulk silicon is etched. Variability in the etch depth translates to undesirable variability in fin height. Such a technique introduces too much variation into the manufacture of variable height fins because the etch process is difficult to precisely control.
Another way to facilitate scaling of CMOS dimensions, while maintaining an acceptable performance, is to increase the mobility of carriers in a semiconductor material. In CMOS technology, n-channel FETs (n-FETs) use electrons as carriers and p-channel FETs (p-FETs) use holes as carriers. When an electric field is applied to a semiconductor substrate, each of the carriers (i.e. holes and electrons) in the substrate will experience a force from the field and will be accelerated along the field. The velocity of the carriers due to this effect is called drift velocity and it is proportional to the applied electric field. This proportionality factor is known as mobility (μ). The higher the mobility, the higher the current density the transistor will have, resulting in a faster switching speed.
In conventional CMOS technologies, mobility of carriers is dependent on a number of factors, especially the surface plane of a wafer. That is, carriers see the periodicity of the atoms (the pattern the atoms form), which is completely determined by the crystal plane. Thus, planar devices always have the mobility associated with the plane on which they are formed.
Accordingly, conventional CMOS technologies use silicon substrates having a surface oriented on a (100) crystal plane. Conventional silicon substrates having a surface oriented on the (100) crystal plane are chosen because: (a) the surface state density between the silicon substrate and the silicon oxide film is at a minimum when the silicon substrate surface is oriented on the (100) plane; and                (b) the mobility of electrons in the (100) plane is higher than in other crystal planes, and therefore, the source-drain current of a n-channel FET formed on the semiconductor substrate having the (100) plane provides the largest current. However, the mobility of holes is not optimized in the (100) plane, and therefore, the source-drain current of a p-channel FET formed on the semiconductor substrate having the (100) plane is inevitably small. The p-channel FET therefore fails to have desirable characteristics, even though the n-channel FET exhibits good characteristics. Many planes in a lattice are equivalent by a symmetry transformation. For example, the (100), (010), and (001) planes are planes of equivalent symmetry. In this application, a plane and all of its equivalent planes are denoted by { } parentheses. Thus, the designation of the plane {100} includes the equivalent (100), (010), and (001) planes. Like the crystal direction, a crystal plane in this application includes both positive and negative integers unless specifically stated or shown otherwise. Accordingly, for example, the designation of the plane {100} includes the (−100), (0–10), and (00–1) planes in addition to the (100), (010), and (001) planes.        
Hole mobility could be enhanced, especially at high electric fields, if p-channel FETs were formed on the (111) plane. However, because the (111) plane has a worse mobility for electrons, it is not used in conventional planar CMOS. In conventional planar CMOS, since utilizing different planes for different devices is impossible (i.e. since planar CMOS is “planar”, both n-channel FETs and p-channel FETs must be on the same plane), the (100) plane provides a compromise between maximizing hole and electron mobility.
Conventional finFET technologies have drawbacks regarding hole mobility. For example, due to mobility differences between electrons and holes in silicon, conventional finFET technologies require the number of p-finFET devices to be approximately twice that of n-finFET devices so to obtain the same electrical current when p-finFET height is the same as n-finFET height. Thus, the total area required for p-finFET devices is approximately twice that of n-finFET devices. Alternatively, conventional techniques for accommodating mobility differences rely on the fabrication of multiple parallel fins on a substrate. This technique has an undesirable circuit density penalty. By fabricating parallel fins for a single device to accommodate mobility differences, one problem is created (more substrate area is consumed per device) while addressing another (mobility differences).
Thus, there is a need for improved finFET technologies that: improve circuit density by forming finFET devices from single fin n-finFETs and from stacked fin p-finFETs without impacting device performance; utilize various crystal planes for FET current channels in order to optimize mobility and/or reduce mobility in specific devices depending upon the particular application; and improve fin height control by forming finFETs from multiple silicon layers having buried oxide layers in between the silicon layers, thus eliminating the need for a silicon etch-stop height control technique.